1. Field of the Invention
This invention relates to a method and an apparatus for modulating or encoding input digital data into DSV-controlled (digital sum value controlled) digital data including information code words and LDPC (low density parity check) code words. In addition, this invention relates to a method and an apparatus for demodulating or decoding LDPC-code-added digital data into original digital data.
2. Description of the Related Art
In general, modulation systems are used for recording digital information signals on recording mediums such as optical discs or magnetic discs. Some modulation systems encode an input data bit stream into an output data bit stream obeying (1, k) RLL which means run length limiting rules such that 1 to k successive bits of “0” should be between bits of “1”. The output data bit stream is recorded on a recording medium. Especially, (1, 7) RLL is the most commonly employed.
The direct-current (DC) component of a (1, 7) RLL information bit stream causes the spectrum of the information bit stream to enter the servo-signal band so that the servo control implemented by a recording-medium drive apparatus (an optical-disc drive apparatus) may be impaired. This problem can be solved by the DSV (digital sum value) control for converging the DSV (digital sum value) of the information bit stream on zero. The DSV convergence on zero results in the suppression of the DC component of the information bit stream.
Japanese patent application publication number 6-195887/1994 discloses a modulation apparatus which receives an information signal divided into sync blocks. Each sync block has a sequence of 174 bytes. In each sync block, the two former bytes are assigned to a sync signal, and the next two bytes are assigned to an ID signal. The remaining 170 bytes are assigned to data (information). The modulation apparatus in Japanese patent application 6-195887/1994 processes the information signal sync-block by sync-block. The processing of the information signal includes pre-coding. Specifically, for each sync block, the modulation apparatus inverts all bits in even-numbered data bytes while keeping unchanged sync bytes, ID bytes, and odd-numbered data bytes. The modulation apparatus combines the inversion-resultant even-numbered data bytes, the sync bytes, the ID bytes, and the odd-numbered data bytes into a pre-coded data bit stream. The modulation apparatus includes a modulation circuit for subjecting the pre-coded data bit stream to (1, 7) RLL modulation to get a modulation-resultant bit stream. The modulation apparatus may invert all bits in even-numbered ID and data bytes while keeping unchanged sync bytes and odd-numbered ID and data bytes. The pre-coding results in the suppression of DC component of the modulation-resultant bit stream.
Japanese patent application publication number 10-340543/1998 discloses an encoding apparatus having a DSV control function. The encoding apparatus in Japanese patent application 10-340543/1998 periodically designates 3 successive bits in a basic (1, 7) RLL data bit stream as an object to be converted for DSV control. The bit in the basic data bit stream which immediately precedes the 3-bit object is defined as a former reference bit. The bit in the basic data bit stream which immediately follows the 3-bit object is defined as a later reference bit. In addition, 6 successive bits immediately following the 3-bit object is defined as a reference bit set. The encoding apparatus converts the 3-bit object into first and second candidate 6-bit DSV control code words in response to the logic states of the former and later reference bits and also the logic state of the reference bit set by referring to a conversion table. Thereby, the encoding apparatus changes the basic data bit stream into first and second conversion-result data bit streams inclusive of the first and second candidate DSV control code words respectively. The encoding apparatus calculates the DSV's of the first and second conversion-result data bit streams up to a bit place significantly later than the positions of the first and second candidate DSV control code words, and compares the calculated DSV's. In accordance with the result of the comparison, the encoding apparatus selects one from the first and second conversion-result data bit streams as a final conversion-result bit stream. In this way, the encoding apparatus implements the DSV control for suppressing the DC component of the final conversion-result bit stream. The conversion of the 3-bit object into the first and second candidate 6-bit DSV control code words is designed so that also the final conversion-result bit stream will obey (1, 7) RLL.
Japanese patent application publication number 2000-105981 discloses a data conversion apparatus which implements 8-12 modulation and DSV control. According to the 8-12 modulation, an input digital signal is divided into 8-bit segments referred to as input code words, and every 8-bit input code word is converted into a 12-bit output code word. A conversion table is used for the conversion of the 8-bit input code word into the 12-bit output code word. The resultant output code words are serially connected to form a word sequence in the shape of a bit stream. In Japanese patent application 2000-105981, the 8-12 modulation is designed so that the output-code-word bit stream will obey (1, 8) RLL. Furthermore, the data conversion apparatus detects every special bit in the output-code-word bit stream, the logic-state inversion of which will not cause the violation of (1, 8) RLL. The data conversion apparatus changes the output-code-word bit stream into a first candidate output bit stream in which the detected special bit remains in its original logic state and a second candidate output bit stream in which the logic state of the detected special bit is inverted from the original. At the time position of a next special bit, the DSV's of the first and second candidate output bit streams are calculated. The absolute values of the calculated DSV's are compared. One of the first and second candidate output bit streams which corresponds to the smaller of the absolute values of the calculated DSV's is selected as a final output bit stream. In this way, the data conversion apparatus implements the DSV control for suppressing the DC component of the final output-code-word bit stream.
Hongwei Song, Jingfeng Liu, and B. V. K. Vijaya Kumar have reported “DC-Free (d, k) Constrained Low Density Parity Check (LDPC) Codes”, ISOM/ODS 2002 (Joint International Symposium on Optical Memory and Optical Data Storage Topical Meeting 2002), Technical Digest 2002 IEEE, pages 377-379. According to the report, a DC-free (1, 7) RLL LDPC code is constructed for low signal-to-noise ratio and high-density recording of data on a recording medium. Specifically, the DC-free (1, 7) RLL LDPC code is generated as follows. The user information bits are first passed through a conventional (1, 7) RLL encoder, and the resultant (1, 7) RLL coded sequence goes through a conventional LDPC encoder. Since the LDPC encoder can be easily made systematic, the information bit part of the LDPC code word satisfies (1, 7) RLL. The resultant LDPC coded sequence is encoded by an extended bit insertion encoder. The extended bit insertion encoder multiplexes the parity check bits with the information bits. Specifically, the extended bit insertion encoder groups the parity check bits into two bits per group and inserts them periodically into the information bits which already satisfy (1, 7) RLL. In more detail, the extended bit insertion encoder groups the parity check bits as two bits P1 and P2 in one group and places a control bit B between the two parity check bits P1 and P2 to make sure that they do not violate “1” run length constraint. If both of the parity check bits P1 and P2 are “0”, then the control bit B is set to “1”. Otherwise, the control bit B is set to “0”. Furthermore, the extended bit insertion encoder generates two control bits A1 and A2 placed immediately before each parity check and control bit set “P1-B-P2”, and two control bits A3 and A4 placed immediately after the bit set “P1-B-P2”. The control bits A1 and A4 are used primarily to ensure that (1, 7) RLL will not be violated. The control bits A2 and A3 are used to control the DC component. There is a straightforward method to control the DC component by selecting the value of the control bits A2 and A3 to control the value of the running digital sum (RDS).
Generally, LDPC codes are excellent in decoding performance and block error rate. Like turbo codes and RA (repeat and accumulate) codes, LDPC codes provide a near-Shannon capacity performance when the code length is great. In addition, LDPC codes hardly cause an error floor phenomenon.
Japanese book, entitled “LDPC (Low Density Parity Check) Codes/Sum-Product Decoding Method”, written by T. Wadayama, published by Triceps in 2002, pages 31-33 and 92-95, discloses an LDPC encoding procedure and a log domain sum-product decoding algorithm. According to the Japanese book, LDPC encoding is implemented by multiplying an information vector and a generation matrix. Specifically, the generation matrix is predetermined, and the product of the information vector and the generation matrix makes LDPC code words. In the case of a systematic code, a parity check matrix for the code is held whose a right-upper triangular area is filled with elements of “0”. A parity check symbol (an LDPC code word) can be derived from an information symbol by using the parity check matrix and iterating backward substitution. In more detail, a combination of the information symbol and the parity check symbol is defined as an output code word. Since the product of the output code word and the transposed version of the parity check matrix is equal to “0”, there is obtained a system of linear equations in which the elements composing the parity check symbol are unknown variables. The linear equation system is solved by reiterating backward substitution, and hence the values of the elements composing the parity check symbol are found.
The log domain sum-product decoding algorithm in the foregoing Japanese book has a repeatable sequence of steps including an updating step and a parity check step. At the parity check step, a decision is made as to whether or not the product of a temporarily estimated code word and the transposed version of the parity check matrix is equal to “0”. When it is decided that the product of the temporarily estimated code word and the transposed version of the parity check matrix is equal to “0”, the temporarily estimated code word is outputted as a final estimated code word. Otherwise, return from the parity check step to the updating step is made, and the updating step updates the temporarily estimated code word.
As previously mentioned, the (1, 7) RLL LDPC code reported by H. Song et al is generated by inserting parity check bits and DC control bits into a sequence of information bits. The implementation of the DC control is difficult when the inserted parity check bits are in specified polarity conditions. Thus, to securely implement the DC control, it is necessary to increase the number of inserted DC control bits. The increase in the number of inserted DC control bits causes a drop in encoding rate.